Phase detectors are well known in the art, for example, as an integral component of a television receiver phase lock loop for providing an output signal representative of the phase error between the mid-pulse of a sync signal and the falling edge of the output signal of a voltage controlled oscillator (VCO). In the phase lock loop example, the output signal of the phase detector is low-pass filtered and applied to the input of the VCO, as is well understood. Most, if not all, phase detectors include a lateral PNP transistor current mirror for sourcing a predetermined current from its output to charge the loop filter. The input and output of the current mirror are typically coupled to the collectors of first and second NPN transistors configured as a differential amplifier having common emitters coupled through a current source operating under control of the sync signal, while the bases of the same are driven by the output signal of the VCO and a reference signal, respectively. The output of the conventional phase detector driving the VCO may be taken at the collector of the second NPN transistor allowing the latter to sink a predetermined current equal to the charging current provided by the PNP transistor current mirror and discharge the loop filter when the oscillator signal is low with respect to the reference signal. Alternately, when the oscillator signal is high with respect to the reference signal, the output current of the PNP transistor current mirror charges the loop filter.
One problem with the lateral PNP transistors is the inherent slower switching speed as compared to the first and second NPN transistors of the differential amplifier, often creating a asymmetrical output current which causes difficulty in achieving phase lock by inducing skew between the edges of the oscillator signal and the mid-pulse of the sync signal, especially in the presence of a noisy VCO oscillator signal. Moreover, it is difficult in most semiconductor processes to achieve good matching between the PNP transistors thereby adding to the asymmetry problem in the output signal of the phase detector. In addition, most integrated circuit processes produce a poor forward transistor current gain, .beta., for the lateral PNP transistors forming the current mirror. Since the phase lock rate is often determined by the charge and discharge rate of the loop filter, the lateral PNP transistors must be sized large to provide a reasonable output current, say 200 microamps. The poor forward transistor current gain enlarges the difference between the input and output currents of the PNP current mirror as the base currents become significant which also induces offset in the output signal. Thus, there is a trade-off between the lock speed of the phase lock loop and the physical area of the conventional phase detector, more specifically, the size of the lateral PNP transistor current mirror. It would be desirable to eliminate the lateral PNP transistors and the undesirable properties associated therewith.
Hence, there is a need for an improved phase detector implemented with an all NPN transistor structure.